Publications

[C44] FormalPCell: Formal DRC Verification of Parameterized Layout Cells via Symbolic Interpretation and SMT Solving

Yuhan Qin, Yuan Pu, Zhuolun He, and Bei Yu.

IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Tokyo, Japan, Jan. 25–28, 2027. To appear

[J13] FabGPT: An Efficient Large Multimodal Model for Complex Wafer Defect Knowledge Queries

Yuqi Jiang, Qian Jin, Xudong Lu, Xiangyue Lyu, Zhuolun He, Xunzhao Yin, Yali Fu, Dawei Gao, Bei Yu, Qi Sun, Hanming Wu, and Cheng Zhuo.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2026.

[J12] CB-EVO: Contextual Bandit Tuning with Evolutionary Search for Logic Synthesis

Fangzhou Liu, Wuqian Tang, Zehua Pei, Ziyang Yu, Haisheng Zheng, Zhuolun He, Mengjia Dai, Tinghuan Chen, and Bei Yu.

ACM Transactions on Design Automation of Electronic Systems (TODAES), 2026.

[J11] Routing-aware Legal Hybrid Bonding Terminal Assignment for 3D Face-to-Face Stacked ICs

Siting Liu, Jieya Zhou, Jiaxi Jiang, Zhuolun He, Ziyi Wang, Yibo Lin, Bei Yu, and Martin Wong.

ACM Transactions on Design Automation of Electronic Systems (TODAES), 2026.

[C43] ChatFCM: Comprehension-Synthesis Decoupling for LLM-Based Functional Coverage Model Generation

Yuan Pu, Yudong He, Zhenghao Chen, Mingjun Wang, Bingkun Yao, Zhaotan Lin, Qin Chen, Bing Li, Song Chen, Zhuolun He, Wenjian Yu, Yanfeng Li, and Bei Yu.

IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, USA, Nov. 8–12, 2026.

[C42] A Multi-Granularity Retrieval Augmented Generation Framework for EDA Tasks Leveraging Knowledge Graph

Yuheng Huang, Yuhan Qin, Yuan Pu, Zhaotan Lin, Yuntao Nie, Zhuolun He, Jianwang Zhai, Kang Zhao, and Bei Yu.

IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, USA, Nov. 8–12, 2026.

[C41] SGLayout: Schema-Guided Closed-Loop Refinement for LLM-Driven Parameterized Layout Generation

Siyang Chen, Yuan Pu, Yuhan Qin, Zhaotan Lin, Siyuan Liang, Zhuolun He, Lining Zhang, and Bei Yu.

IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, USA, Nov. 8–12, 2026.

[C40] One-Token Rollout: Guiding Supervised Fine-Tuning of LLMs with Policy Gradient

Rui Ming, Haoyuan Wu, Shoubo Hu, Zhuolun He, and Bei Yu.

Empirical Methods in Natural Language Processing (EMNLP), Budapest, Hungary, Oct. 24–29, 2026.

[C39] S-Quant: Rethinking Weight Quantization with Seed-Based Generation

Mingzi Wang, Lancheng Zou, Shuo Yin, Zhuolun He, and Bei Yu.

International Conference on Machine Learning (ICML), Seoul, South Korea, Jul. 6–11, 2026.

[Paper]

[C38] MAEDA: An LLM-Powered Multi-Agent Evaluation Framework for EDA Tool Documentation QA

Zhenghao Chen, Yuan Pu, Hairuo Han, Yuntao Nie, Jiajun Qin, Yuhan Qin, Tairu Qiu, Zhuolun He, Jianwang Zhai, Bei Yu, and Kang Zhao.

IEEE/ACM Proceedings Design, Automation and Test in Europe (DATE), Verona, Italy, Apr. 20–22, 2026.

[Paper]

[C37] Infusing EDA Knowledge into LLM Systems: An Information-Source Perspective

Yuhan Qin, Yuan Pu, Tairu Qiu, Zhuolun He, and Bei Yu.

ACM International Symposium on Physical Design (ISPD), Bonn, Germany, Mar. 15–18, 2026. Invited Paper

[Paper][Poster]

[C36] CombRewriter: Enabling Combinational Logic Simplification in MLIR-Based Hardware Compiler

Haisheng Zheng, Zhuolun He, Shuo Yin, Yuzhe Ma, and Bei Yu.

IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Hong Kong, Jan. 19–22, 2026.

[Paper][Poster]

[J10] Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QA

Yuan Pu, Zhuolun He, Yuqi Jiang, Tairu Qiu, Haoyuan Wu, Qi Sun, Cheng Zhuo, and Bei Yu.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2025.

[J9] Large Language Models for EDA: Future or Mirage?

Zhuolun He, Yuan Pu, Haoyuan Wu, Tairu Qiu, and Bei Yu.

ACM Transactions on Design Automation of Electronic Systems (TODAES), 2025. Editor's Pick

[J8] EasyMRC: Efficient Mask Rule Checking via Representative Edge Sampling

Jiahao Xu, Zhuolun He, Shuo Yin, Yuan Pu, Wenjian Yu, and Bei Yu.

ACM Transactions on Design Automation of Electronic Systems (TODAES), 2025.

[J7] IncreMacro: Incremental Macro Placement Refinement

Yuan Pu, Tinghuan Chen, Zhuolun He, Jiajun Qin, Chen Bai, Haisheng Zheng, Yibo Lin, and Bei Yu.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2025.

[J6] Large Language Models for EDA: From Assistants to Agents

Zhuolun He, Yuan Pu, Haoyuan Wu, Yuhan Qin, Tairu Qiu, and Bei Yu.

Foundations and Trends in Electronic Design Automation, 2025.

[J5] FGNN2: A Powerful Pre-training Framework for Learning the Logic Functionality of Circuits

Ziyi Wang, Chen Bai, Zhuolun He, Guangliang Zhang, Qiang Xu, Tsung-Yi Ho, Yu Huang, and Bei Yu.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2025.

[Paper][Code]

[C35] On-Policy Optimization with Group Equivalent Preference for Multi-Programming Language Understanding

Haoyuan Wu, Rui Ming, Jilong Gao, Hangyu Zhao, Xueyi Chen, Yikai Yang, Haisheng Zheng, Zhuolun He, and Bei Yu.

Neural Information Processing Systems (NeurIPS), San Diego, CA, USA, Dec. 2–7, 2025.

[Paper][Poster]

[C34] GPU Acceleration for Versatile Buffer Insertion

Yuan Pu, Yuhao Ji, Siying Yu, Zuodong Zhang, Zizheng Guo, Zhuolun He, Yibo Lin, David Z. Pan, and Bei Yu.

IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Munich, Germany, Oct. 26–30, 2025.

[Paper][Slides]

[C33] MM-GRADE: A Multi-Modal EDA Tool Documentation QA Framework Leveraging Retrieval Augmented Generation

Yuan Pu, Zhuolun He, Shutong Lin, Jiajun Qin, Xinyun Zhang, Hairuo Han, Haisheng Zheng, Yuqi Jiang, Cheng Zhuo, Qi Sun, David Z. Pan, and Bei Yu.

IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Munich, Germany, Oct. 26–30, 2025.

[Paper][Slides]

[C32] Efficient OpAmp Adaptation for Zoom Attention to Golden Contexts

Haoyuan Wu, Rui Ming, Haisheng Zheng, Zhuolun He, and Bei Yu.

Association for Computational Linguistics (ACL), Vienna, Austria, Jul. 27–Aug. 1, 2025.

[Paper][Slides][Poster]

[C31] ChatLS: Multimodal Retrieval-Augmented Generation and Chain-of-Thought for Logic Synthesis Script Customization

Haisheng Zheng, Haoyuan Wu, and Zhuolun He.

ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, Jun. 22–25, 2025.

[Paper][Slides][Poster]

[C30] Swift or Exact? Boosting Efficient Microarchitecture DSE via Multi-fidelity Partial Order Prediction

Hang Liu, Hao Geng, Zhuolun He, Qi Sun, and Cheng Zhuo.

ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, Jun. 22–25, 2025.

[C29] Divergent Thoughts toward One Goal: LLM-based Multi-Agent Collaboration System for Electronic Design Automation

Haoyuan Wu, Haisheng Zheng, Zhuolun He, and Bei Yu.

Nations of the Americas Chapter of the Association for Computational Linguistics (NAACL), Albuquerque, NM, USA, Apr. 29–May 2, 2025.

[Paper][Poster]

[C28] iRw: An Intelligent Rewriting

Haisheng Zheng, Haoyuan Wu, Zhuolun He, Yuzhe Ma, and Bei Yu.

IEEE/ACM Proceedings Design, Automation and Test in Europe (DATE), Lyon, France, Mar. 31–Apr. 2, 2025.

[Paper][Slides][Poster]

[C27] HeLO: A Heterogeneous Logic Optimization Framework by Hierarchical Clustering and Graph Learning

Yuan Pu, Fangzhou Liu, Zhuolun He, Keren Zhu, Rongliang Fu, Ziyi Wang, Tsung-Yi Ho, and Bei Yu.

ACM International Symposium on Physical Design (ISPD), Austin, TX, USA, Mar. 16–19, 2025. Best Paper Award Nomination

[Paper][Slides]

[J4] ChatEDA: A Large Language Model Powered Autonomous Agent for EDA

Haoyuan Wu, Zhuolun He, Xinyun Zhang, Xufeng Yao, Su Zheng, Haisheng Zheng, and Bei Yu.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2024.

[Paper]

[C26] Parameter-Efficient Sparsity Crafting from Dense to Mixture-of-Experts for Instruction Tuning on General Tasks

Haoyuan Wu, Haisheng Zheng, Zhuolun He, and Bei Yu.

Empirical Methods in Natural Language Processing (EMNLP), Miami, FL, USA, Dec. 12–16, 2024.

[Paper][Slides][Poster]

[C25] Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QA

Yuan Pu, Zhuolun He, Tairu Qiu, Haoyuan Wu, and Bei Yu.

IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Newark, NJ, USA, Oct. 27–31, 2024. Best Paper Award Nomination

[Paper][Slides]

[C24] Lesyn: Placement-aware Logic Resynthesis for Non-Integer Multiple-Cell-Height Designs

Yuan Pu, Fangzhou Liu, Yu Zhang, Zhuolun He, Kai-Yuan Chao, Yibo Lin, and Bei Yu.

ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, Jun. 23–27, 2024.

[Paper][Slides]

[C23] PDRC: Package Design Rule Checking via GPU-Accelerated Geometric Intersection Algorithms for Non-Manhattan Geometry

Jiaxi Jiang, Lancheng Zou, Wenqian Zhao, Zhuolun He, Tinghuan Chen, and Bei Yu.

ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, Jun. 23–27, 2024.

[Paper][Slides]

[C22] CBTune: Contextual Bandit Tuning for Logic Synthesis

Fangzhou Liu, Zehua Pei, Ziyang Yu, Haisheng Zheng, Zhuolun He, Tinghuan Chen, and Bei Yu.

IEEE/ACM Design, Automation and Test in Europe Conference (DATE), Valencia, Spain, Mar. 25–27, 2024.

[Paper][Slides][Poster]

[C21] Large Language Models for EDA: Future or Mirage?

Zhuolun He and Bei Yu.

ACM International Symposium on Physical Design (ISPD), Taipei, Mar. 12–15, 2024.

[Paper]

[C20] IncreMacro: Incremental Macro Placement Refinement

Yuan Pu, Tinghuan Chen, Zhuolun He, Chen Bai, Haisheng Zheng, Yibo Lin, and Bei Yu.

ACM International Symposium on Physical Design (ISPD), Taipei, Mar. 12–15, 2024. Best Paper Award Nomination

[Paper][Slides]

[C19] Routing-aware Legal Hybrid Bonding Terminal Assignment for 3D Face-to-Face Stacked ICs

Siting Liu, Jiaxi Jiang, Zhuolun He, Ziyi Wang, Yibo Lin, and Bei Yu.

ACM International Symposium on Physical Design (ISPD), Taipei, Mar. 12–15, 2024.

[Paper][Slides]

[C18] LSTP: A Logic Synthesis Timing Predictor

Haisheng Zheng, Zhuolun He, Fangzhou Liu, Zehua Pei, and Bei Yu.

IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Incheon, South Korea, Jan. 22–25, 2024.

[Paper][Slides]

[J3] Efficient Super-Resolution System with Block-wise Hybridization and Quantized Winograd on FPGA

Bizhao Shi, Jiaxi Zhang, Zhuolun He, Xuechao Wei, Sicheng Li, Guojie Luo, Hongzhong Zheng, and Yuan Xie.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2023.

[J2] Efficient Arithmetic Block Identification with Graph Learning and Network-flow

Ziyi Wang, Zhuolun He, Chen Bai, Haoyu Yang, and Bei Yu.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2023.

[C17] Heterogenous Acceleration for Design Rule Checking

Zhuolun He and Bei Yu.

IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Francisco, CA, USA, Oct. 29–Nov. 2, 2023. Invited Paper

[Paper][Slides]

[C16] AlphaSyn: Logic Synthesis Optimization with Efficient Monte Carlo Tree Search

Zehua Pei, Fangzhou Liu, Zhuolun He, Guojin Chen, Haisheng Zheng, Keren Zhu, and Bei Yu.

IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Francisco, CA, USA, Oct. 29–Nov. 2, 2023.

[Paper][Slides][Poster]

[C15] ChatEDA: A Large Language Model Powered Autonomous Agent for EDA

Zhuolun He, Haoyuan Wu, Xinyun Zhang, Xufeng Yao, Su Zheng, Haisheng Zheng, and Bei Yu.

ACM/IEEE Workshop on Machine Learning for CAD (MLCAD), Snowbird, UT, USA, Sept. 11–13, 2023.

[Paper][arXiv]

[C14] OpenDRC: An Efficient Open-Source Design Rule Checking Engine with Hierarchical GPU Acceleration

Zhuolun He, Yihang Zuo, Jiaxi Jiang, Haisheng Zheng, Yuzhe Ma, and Bei Yu.

ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, Jul. 9–13, 2023.

[Paper][Slides]

[C13] Bit-Level Quantization for Efficient Layout Hotspot Detection

Zehua Pei, Wenqian Zhao, Zhuolun He, and Bei Yu.

International Symposium of Electronics Design Automation (ISEDA), Nanjing, China, May 9–11, 2023.

[Paper]

[C12] Enabling Efficient Design Rule Checking with GPU Acceleration

Wei Zhong, Zhenhua Feng, Zhuolun He, Weimin Wang, Yuzhe Ma, and Bei Yu.

IEEE/ACM Proceedings Design, Automation and Test in Europe (DATE), Antwerp, Belgium, Apr. 17–19, 2023. extended abstract

[Paper]

[C11] AutoGraph: Optimizing DNN Computation Graph for Parallel GPU Kernel Execution

Yuxuan Zhao, Qi Sun, Zhuolun He, Yang Bai, and Bei Yu.

AAAI Conference on Artificial Intelligence (AAAI), Washington, DC, USA, Feb. 7–14, 2023.

[Paper][Slides]

[C10] X-Check: GPU-Accelerated Design Rule Checking via Parallel Sweepline Algorithms

Zhuolun He, Yuzhe Ma, and Bei Yu.

IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Diego, CA, USA, Oct. 30–Nov. 3, 2022.

[Paper][Slides]

[C9] Functionality Matters in Netlist Representation Learning

Ziyi Wang, Chen Bai, Zhuolun He, Guangliang Zhang, Qiang Xu, Tsung-Yi Ho, Bei Yu, and Yu Huang.

ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, Jul. 10–14, 2022.

[Paper][Slides]

[C8] Graph Learning-Based Arithmetic Block Identification

Zhuolun He, Ziyi Wang, Chen Bai, Haoyu Yang, and Bei Yu.

IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Munich, Germany, Nov. 1–4, 2021.

[Paper][Slides]

[C7] Physical Synthesis for Advanced Neural Network Processors

Zhuolun He, Peiyu Liao, Siting Liu, Yuzhe Ma, and Bei Yu.

IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Tokyo, Japan, Jan. 18–21, 2021. Invited Paper

[Paper][Slides]

[C6] Reinforcement Learning Driven Physical Synthesis

Zhuolun He, Lu Zhang, Peiyu Liao, Yuzhe Ma, and Bei Yu.

IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Kunming, China, Nov. 3–6, 2020. Invited Paper

[Paper]

[C5] Hotcake: Higher order tucker articulated kernels for deeper CNN compression

Rui Lin, Ching-Yun Ko, Zhuolun He, Cong Chen, Yuan Cheng, Hao Yu, Graziano Chesi, and Ngai Wong.

IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Kunming, China, Nov. 3–6, 2020. Invited Paper

[Paper]

[C4] Learn to Floorplan through Acquisition of Effective Local Search Heuristics

Zhuolun He, Yuzhe Ma, Lu Zhang, Peiyu Liao, Ngai Wong, Bei Yu, and Martin D.F. Wong.

IEEE International Conference on Computer Design (ICCD), Hartford, CT, USA, Oct. 18–21, 2020.

[Paper][Slides]

[C3] Understanding Graphs in EDA: From Shallow to Deep Learning

Yuzhe Ma, Zhuolun He, Wei Li, Tinghuan Chen, Lu Zhang, and Bei Yu.

ACM International Symposium on Physical Design (ISPD), Taipei, Mar. 25–Apr. 1, 2020. Invited Paper

[Paper]

[J1] Deep Model Compression and Inference Speedup of Sum-Product Networks on Tensor Trains

Ching-Yun Ko, Cong Chen, Zhuolun He, Yuke Zhang, Kim Batselier, and Ngai Wong.

IEEE Transactions on Neural Networks and Learning Systems (TNNLS), 2019.

[C2] FPGA-based Real-time Super-resolution System for Ultra High Definition Videos

Zhuolun He, Hanxian Huang, Ming Jiang, Yuanchao Bai, and Guojie Luo.

IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), Boulder, CO, USA, Apr. 29–May 1, 2018.

[Paper][Slides]

[C1] FPGA Acceleration for Computational Glass-Free Displays

Zhuolun He and Guojie Luo.

ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), Monterey, CA, USA, Feb. 22–24, 2017.

[Paper][Slides]